A bipolar junction transistor (“BJT”), often referred to simply as a bipolar transistor, is a semiconductor device in which a base extends between an emitter and a collector. The base is formed with semiconductor material of one conductivity type, namely p-type for an npn BJT and n-type for a pnp BJT where the middle letter of the acronym “npn” or “pnp” identifies the conductivity type of the base. The emitter and collector are formed with semiconductor material of the opposite conductivity type, i.e., n-type for the npn BJT and p-type for the pnp BJT. Current flows through an npn BJT when its base-to-emitter voltage VBE reaches a positive threshold value VBE0 typically in the vicinity of 0.7 V. Similarly, current flows through a pnp BJT when its base-to-emitter voltage VBE reaches a negative threshold value VBE0 typically in the vicinity of −0.7 V.
An IGFET is a semiconductor device in which a gate dielectric layer electrically insulates a gate electrode from a channel zone extending between a source zone and a drain zone. The channel zone in an enhancement-mode IGFET is part of a body region, often termed the substrate or substrate region, which forms respective pn junctions with the source and drain. In an enhancement-mode IGFET, the channel zone consists of all the semiconductor material between the source and drain. During IGFET operation, charge carriers move from the source to the drain through a channel induced in the channel zone along the upper semiconductor surface. The threshold voltage is the value of the gate-to-source voltage at which the IGFET starts to conduct current for a given definition of the threshold (minimum) conduction current. The channel length is the distance between the source and drain along the upper semiconductor surface.
The term “mixed signal” refers to integrated circuits (“ICs”) containing both digital and analog circuitry blocks. The digital circuitry typically employs the most aggressively scaled n-channel and p-channel IGFETs for obtaining the maximum potential digital speed at given current leakage specifications. The analog circuitry utilizes IGFETs and/or BJTs subjected to different performance requirements than the digital IGFETs. Requirements for the analog IGFETs commonly include high linear voltage gain, good small-signal and large-signal frequency response at high frequency, good parameter matching, low input noise, well controlled electrical parameters for active and passive components, and reduced parasitics, especially reduced parasitic capacitances. Although it would be economically attractive to utilize the same transistors for the analog and digital blocks, doing so would typically lead to weakened analog performance. Many requirements imposed on analog IGFET performance conflict with the results of digital scaling.
Digital circuitry blocks predominantly use the smallest IGFETs that can be fabricated. Because the resultant dimensional spreads are inherently large, parameter matching in digital circuitry is often relatively poor. In contrast, good parameter matching is usually needed in analog circuitry to achieve the requisite performance. This typically requires that analog transistors be fabricated at greater dimensions than digital IGFETs subject to making analog IGFETS as short as possible in order to have source-to-drain propagation delay as low as possible.
IGFETs are the predominate type of transistors in current ICs. As a result, fabrication of an IC containing IGFETs and BJTs is typically directed primarily toward optimizing the IGFET characteristics. Optimization of the BJT characteristics is then performed subject to substantially maintaining the optimized characteristics of the IGFETs. Alvarez, BiCMOS Technology and Applications (2d ed., Kluwer Acad. Publishers), 1993, pages 75-78, describes this IC fabrication approach.
FIG. 1 illustrates a conventional single-well complementary-IGFET (“CIGFET”) semiconductor structure as described in Alvarez. This CIGFET semiconductor structure, commonly referred to as “CMOS”, serves as a basis for more advanced semiconductor structures that contain complementary IGFETs and BJTs. The single-well CIGFET structure of FIG. 1 contains symmetric n-channel IGFET 20 and symmetric p-channel IGFET 22 fabricated from a semiconductor body consisting of heavily doped p-type monocrystalline silicon (“monosilicon”) substrate 24 and overlying lightly doped p-type monosilicon epitaxial layer 26. Recessed field region 28 of electrically insulating material, primarily silicon oxide, extends along the upper surface of p-epitaxial layer 26 to define laterally separated semiconductor islands 30 and 32.
N-channel IGFET 20 contains surface-adjoining heavily doped n-type source/drain (“S/D”) zones 34 and 36 situated in island 32 and laterally separated by a channel zone of p-type body material that includes p− epitaxial layer 26. Gate dielectric layer 40 vertically separates the p-type channel zone from doped polycrystalline silicon (“polysilicon”) gate electrode 42 of IGFET 20. P-channel IGFET 22 contains surface-adjoining heavily doped p-type S/D zones 44 and 46 situated in island 32 and laterally separated by a channel zone of n-type body material consisting of moderately doped n-type well region 48 formed in p− epitaxial layer 26. Gate dielectric layer 50 vertically separates the n-type channel zone from doped polysilicon gate electrode 52 of IGFET 22.
Monosilicon regions 34, 36, 44, 46, and 48 are defined by a series of photoresist masking/doping operations. These processing operations could also be utilized to form lateral and vertical BJTs. For instance, the p-type emitter of a vertical pnp transistor could be defined by the masking/doping operation used to form p+ S/D zones 44 and 46 of p-channel IGFET 22. The masking/doping operation used to form n well region 52 of IGFET 22 in combination with the masking/doping operations used to form p+ S/D zones 44 and 46 would then be employed to define the n-type base of the vertical pnp transistor. P+ substrate 24 and p− epitaxial layer 26 would serve as the transistor's collector. However, the vertical pnp transistor would generally have relatively weak operating characteristics. The same applies to lateral BJTs defined only with the processing steps employed to form IGFETs 20 and 22.
FIG. 2 illustrates, as generally described in Alvarez, how the single-well CIGFET structure of FIG. 1 is extended in a conventional rudimentary manner to include vertical npn BJT 33, thereby forming a single-well BJT/CIGFET semiconductor structure. Recessed field-oxide layer 30 in this semiconductor structure, commonly referred to as “BiCMOS”, defines laterally separated semiconductor islands 35 and 37. Npn transistor 33 consists of (a) surface-adjoining heavily doped n-type emitter 39 situated in island 35, (b) a p-type base largely situated in island 35 so as to underlie and laterally surround n+ emitter 39, and (c) an n-type collector formed in p− epitaxial layer 26 so as to extend from the base, below field oxide 28, and into island 37 up to the upper semiconductor surface.
The p-type base includes moderately doped intrinsic base portion 41I and an extrinsic base zone formed with moderately doped base link portion 41L and surface-adjoining heavily doped base contact portion 41C. P base link portion 41L is continuous with p intrinsic base portion 41I and extends between n+ emitter 39 and p+ base contact portion 41C. The n-type collector consists of heavily doped collector contact portion 43C and moderately doped main collector portion 43M which extends from n+ collector contact portion 43C to the p-type base, particularly to intrinsic portion 41I.
Voltages for controlling npn transistor 31 are variously applied to emitter 39, base contact portion 41C, and collector contact portion 43C through suitable electrical contacts (not shown). The voltage at base contact portion 41C is transmitted through base link portion 41L to intrinsic base portion 41I. During operation, current in the form of electrons flows from emitter 39, vertically downward through intrinsic base portion 41I, laterally through main collector portion 43M, and upward to collector contact portion 43C.
During the fabrication of the BJT/CIGFET structure of FIG. 2, n+ emitter 39 and n+ collector contact portion 43C are formed with the same steps as n+ S/D zones 36 and 38 of re-channel IGFET 20. P+ base contact portion 41C is formed with the same steps as p+ S/D zones 46 and 48 of p-channel IGFET 22. N main collector portion 43M is formed with the same steps as n well region 48 of IGFET 22. The only additional processing needed to convert the CMOS structure of FIG. 1 into the BJT/CIGFET structure of FIG. 2 is a masking/doping operation to create the combination of p intrinsic base portion 41I and p base link portion 41L.
The length LBL of base link portion 41L, i.e., the distance between n+ emitter 39 and p+ base contact portion 41C along the upper semiconductor surface, is defined by the edges of the photoresist masks utilized in defining emitter 39 and base contact portion 41C. The photoresist mask used in forming emitter 39 is also used in forming n+ S/D zones 34 and 36 of n-channel IGFET 20 and is non-critical with respect to S/D zones 34 and 36 because their lateral extents are determined by lateral edges of recessed field-oxide region 28 and gate electrode 42. Similarly, the photoresist mask used in forming base contact portion 41C is also used in forming p+ S/D zones 44 and 46 of p-channel IGFET 22 and is non-critical with respect to S/D zones 44 and 46 because their lateral extents are determined by lateral edges of field oxide 28 and gate electrode 52.
The additional masking/doping operation employed to form intrinsic base portion 41I and base link portion 41L enables the operating characteristics of npn transistor 33 to be improved. However, the n-type doping in main collector portion 43M is normally so low that the collector resistance is relatively high. This limits the usefulness of npn transistor 33.
FIG. 3 illustrates, again as generally described in Alvarez, a conventional single-well BJT/CIGFET semiconductor structure that overcomes the high collector resistance problem. The BJT/CIGFET structure of FIG. 3 contains n-channel IGFET 20V, p-channel IGFET 22V, and npn BJT 33V configured respectively the same as transistors 20, 22, and 33 except as described below. P+ substrate 24 and p− epitaxial layer 26 in the BJT/CIGFET structure of FIG. 2 are replaced here with lightly doped p-type monosilicon substrate 54 and overlying moderately doped n-type monosilicon epitaxial layer 56. The p-type body material for n-channel IGFET 20V includes moderately doped well region 58 formed largely in n epitaxial layer 56. The n-type body material for p-channel IGFET 22V consists of (a) segment 60M of epitaxial layer 56 and (b) heavily doped buried layer 60B formed the along the interface between p− substrate 54 and epitaxial layer 56.
The n-type collector of npn transistor 33V is constituted with (a) segment 61M of epitaxial layer 56, (b) heavily doped buried collector layer 61B formed along the interface (indicated in dashed line in FIG. 3) between substrate 54 and epitaxial layer 56, and (c) heavily doped collector contact portion 61C which extends from n+ buried layer 61B through semiconductor island 37 to the upper semiconductor surface. The heavy dopings of n+ buried collector layer 61B and n+ collector contact portion 61C substantially reduce the collector resistance. Additionally, moderately doped p-type well region 62 is situated between n epitaxial segments 60M and 61M so as to laterally isolate npn transistor 33V from p-channel IGFET 22V.
During the fabrication of the BJT/CIGFET structure of FIG. 3, n+ buried collector layer 61B is formed with the same steps as n+ buried layer 60B for IGFET 22V. Isolating p well 62 is formed with the same steps as p well 58 for IGFET 20V. The change from n well region 48 and simultaneously formed main collector portion 43M in the BJT/CIGFET structure of FIG. 2 to simultaneously formed p wells 58 and 62 in the BJT/CIGFET structure of FIG. 3 does not involve any significant additional fabrication steps. However, the formation of n+ buried layers 61B and 60B requires an additional masking/doping operation. The formation of n+ collector contact portion 61C requires another additional masking/doping operation. Consequently, the reduction in the collector resistance in the BJT/CIGFET structure of FIG. 3 is achieved at the expense of two additional masking/doping operations.
A further advanced conventional BJT/CIGFET semiconductor structure, once again as generally described in Alvarez, is illustrated in FIG. 4. This BJT/CIGFET structure is a twin-well structure containing n-channel IGFET 20W, p-channel IGFET 22W, and npn BJT 33W configured respectively the same as transistors 20V, 22V, and 33V except as described below. N-epitaxial layer 58 in the BJT/CIGFET structure of FIG. 3 is replaced here with near intrinsic monosilicon epitaxial layer 63. Recessed field-oxide region 28 in the BJT/CIGFET structure of FIG. 3 is replaced here with recessed field-oxide region 28W of reduced height above the upper semiconductor surface.
The p-type body material for n-channel IGFET 20W includes (a) moderately doped well region 64W formed in intrinsic epitaxial layer 63, (b) moderately doped buried layer 64B formed along the interface (not indicated in FIG. 4) between p− substrate 54 and epitaxial layer 63, and (c) surface-adjoining heavily doped body contact portion 64C. Each n+ S/D zone 34 or 36 in the BJT/CIGFET structure of FIG. 3 is replaced here with an n-type S/D zone 34W or 36W consisting of a heavily doped main portion and a more lightly doped lateral extension. Dielectric spacers 66 and 68 are situated along the sidewalls of polysilicon gate electrode 42.
The n-type body material for p-channel IGFET 22W is formed with (a) moderately doped well region 70W formed in epitaxial layer 63, (b) moderately doped buried layer 70B formed along the interface between substrate 54 and epitaxial layer 63, and (c) surface-adjoining heavily doped body contact portion 70C. Channel portion 72, apparently of p-type conductivity, extends between p-type S/D zones 44W and 46W. IGFET 22W therefore appears to be a depletion-mode device. Dielectric spacers 76 and 78 are situated along the sidewalls of polysilicon gate electrode 52.
The n-type collector of npn transistor 33W consists of (a) segment 65M of epitaxial layer 63, (b) heavily doped buried collector layer 65B formed along the interface between substrate 54 and epitaxial layer 63, and (c) heavily doped collector contact portion 65C which extends from n+ buried collector layer 65B through semiconductor island 37 to the upper semiconductor surface. As with n+ buried collector layer 61B and n+ collector contact portion 61C in the BJT/CIGFET structure of FIG. 3, the heavy dopings of n+ buried collector layer 65B and n+ collector contact portion 65C here substantially reduce the collector resistance. The combination of polysilicon-filled deep trench 67 and underlying heavily doped p-type anti-inversion region 69 laterally isolates npn transistor 33 from p-channel IGFET 22.
Electrically insulating layer 71 extends over n+ monosilicon portion 39 of the n-type emitter of npn transistor 33W. Doped n-type polysilicon portion 73 of the emitter contacts monosilicon emitter portion 39 through an access opening in insulating layer 71. Dielectric spacers 75 and 77 are situated along the sidewalls of polysilicon emitter portion 73. Finally, metal silicide layers, indicated in slanted-line shading but (to avoid further illustration complexity) lacking reference notation, are situated along the tops of base contact portion 41C, collector contact portion 43C, polysilicon emitter portion 73, S/D zones 34W, 36W, 44W, and 46W, and gate electrodes 42 and 52.
The BJT/CIGFET structure of FIG. 4 provides considerably better operating characteristics for transistors 20W, 22W, and 33W in exchange for additional processing complexity. Of note, n+ monosilicon emitter portion 39 is formed by dopant outdiffusion from polysilicon emitter portion 73 subsequent to performing a masking/etching operation to create the emitter access opening through insulating layer 71 and forming polysilicon emitter portion 73. After forming emitter-adjoining sidewall spacers 75 and 77, base contact portion 41C is created with the same steps as S/D zones 44 and 46 of p-channel IGFET 22W. In particular, a masking/doping operation is performed utilizing emitter-contact spacer 75 as part of the overall mask. Base-link length LBL, again the distance between monosilicon emitter portion 39 and base contact portion 41C, is therefore defined here by the combination of (a) the lateral thickness of emitter-contact spacer 75 and the closest edge of the opening in the photoresist mask used in forming the emitter access opening through insulating layer 71.
Base-link length LBL needs to be well controlled. The emitter-base junction of a BJT can break down prematurely during transistor operation if base-link length LBL is too small. Since base-link length LBL in the BJT/CIGFET structures of FIGS. 2 and 3 is defined by photoresist masks which are non-critically used in forming S/D zones 34, 36, 44, and 46, the ability to control base-link length LBL is dependent on the lithographic alignment capability of photoresist masks that are non-critical from a CIGFET aspect. This raises a significant reliability concern. While this reliability concern is somewhat alleviated in fabricating the BJT/CIGFET structure of FIG. 4, the BJT/CIGFET structure of FIG. 4 is considerably more specialized than those of FIGS. 2 and 3.
It would be desirable to have a semiconductor technology that includes a technique for precisely controlling base-link length LBL in a manner independent of lithographic masking capability differences between IGFETs and BJTs. In particular, the technique for controlling base-link length LBL should be critical in the fabrication of both IGFETs and BJTs. It would also be desirable for the semiconductor technology to provide transistors with good analog characteristics as well as transistors for high-performance digital applications.